Product Overview of Semi-Insulating SiC Wafers

High-Purity Semi-Insulating SiC Wafers are engineered for next-generation power electronics, RF/microwave devices, and optoelectronics. Our wafers are fabricated from 4H- or 6H-SiC single crystals using an optimized Physical Vapor Transport (PVT) growth process combined with deep-level compensation annealing. The result is a wafer with:

• Ultra-High Resistivity: ≥1×10¹² Ω·cm, to suppress leakage currents in high-voltage switching devices

• Wide Bandgap (~3.2 eV): Maintains superior electrical performance under high-temperature, high-field, and high-radiation conditions

• Exceptional Thermal Conductivity: >4.9 W/cm·K, for rapid heat removal in high-power modules

• Outstanding Mechanical Strength: Mohs hardness of 9.0 (second only to diamond), low thermal expansion, and excellent chemical stability

• Atomically Smooth Surface: Ra < 0.4 nm with defect density < 1/cm², ideal for MOCVD/HVPE epitaxy and micro-nano fabrication

Available Sizes: 50, 75, 100, 150, 200 mm (2″–8″) standard; custom diameters up to 250 mm on request.
Thickness Range: 200–1 000 μm with ±5 μm tolerance.

Manufacturing Principles & Process Flow of Semi-Insulating SiC Wafers

1. High-Purity SiC Powder Preparation

    

    

    

    

    

   • Starting material: 6N–grade SiC powder purified via multi-stage vacuum sublimation and thermal treatment to reduce metal contaminants (Fe, Cr, Ni < 10 ppb) and eliminate polycrystalline inclusions.

2. Modified PVT Single-Crystal Growth

    

    

    

   • Environment: 10⁻³–10⁻² Torr near-vacuum

   • Temperature: Graphite crucible heated to ~2 500 °C; controlled thermal gradient ΔT ≈ 10–20 °C/cm

   • Gas Flow & Crucible Design: Porous graphite separators and tailored crucible geometry ensure uniform vapor distribution and inhibit unwanted nucleation

   • Dynamic Feed & Rotation: Periodic SiC powder replenishment and crystal-rod rotation yield low dislocation densities (< 3 000 cm⁻²) and consistent 4H/6H orientation

3. Deep-Level Compensation Annealing

    

    

    

    

   • Hydrogen Anneal: 600–1 400 °C in H₂ atmosphere for several hours to activate deep-level traps and compensate intrinsic carriers

   • N/Al Co-Doping (Optional): Precise incorporation of Al (acceptor) and N (donor) dopants during growth or post-growth CVD to create stable donor-acceptor pairs, driving resistivity peaks

4. Precision Slicing & Multi-Stage Lapping

    

    

    

   • Diamond-Wire Sawing: Slices wafers to 200–1 000 μm thickness with minimal damage layer; thickness tolerance ±5 μm

   • Coarse to Fine Lapping: Sequential use of diamond abrasives to remove sawing damage and prepare for polishing

5. Chemical Mechanical Polishing (CMP)

    

    

    

   • Polishing Media: Nano-oxide (SiO₂ or CeO₂) slurry in a mild alkaline suspension

   • Process Control: Low-stress polishing parameters deliver RMS roughness of 0.2–0.4 nm and eliminate micro-scratches

6. Final Cleaning & Class-100 Packaging

   • Multi-Step Ultrasonic Cleaning: Organic solvent → acid/base treatments → deionized water rinse, all performed in a Class-100 cleanroom

   • Drying & Sealing: Nitrogen purge drying, sealed in nitrogen-filled protective bags, and housed in anti-static, vibration-dampening outer boxes

Key Application Areas of Semi-Insulating SiC Wafers

• High-Power Electronics

  • SiC MOSFETs, Schottky diodes, high-voltage inverters, and fast-charging EV power modules leverage SiC’s low on-resistance and high breakdown field.

• RF & Microwave Systems

  • 5G/6G base-station power amplifiers, millimeter-wave radar modules, and satellite communication front-ends demand SiC’s high-frequency performance and radiation hardness.

• Optoelectronics & Photonics

  • UV-LEDs, blue-laser diodes, and wide-bandgap photodetectors benefit from an atomically smooth and defect-free substrate for uniform epitaxy.

• Extreme Environment Sensing

  • High-temperature pressure/temperature sensors, gas-turbine monitoring elements, and nuclear-grade detectors exploit SiC’s stability above 600 °C and under high radiation flux.

• Aerospace & Defense

  • Satellite power electronics, missile-borne radars, and avionic systems require SiC’s robustness in vacuum, temperature cycling, and high-G environments.

• Advanced Research & Custom Solutions

  • Quantum computing isolation substrates, micro-cavity optics, and bespoke window shapes (spherical, V-groove, polygonal) for cutting-edge R&D.

Frequently Asked Questions (FAQ) of Semi-Insulating SiC Wafers

1. Why choose semi-insulating SiC over conductive SiC?
   Semi-insulating SiC exhibits ultra-high resistivity via deep-level compensation, greatly reducing leakage currents in high-voltage and high-frequency devices, whereas conductive SiC is suited for lower-voltage or power MOSFET channel applications.

2. Can these wafers go straight into epitaxial growth?
   Yes. We offer “epi-ready” semi-insulating wafers optimized for MOCVD, HVPE, or MBE, complete with surface treatment and defect control to ensure excellent epitaxial layer quality.

3. How is wafer cleanliness guaranteed?
   A Class-100 cleanroom process, multi-step ultrasonic and chemical cleaning, plus nitrogen-sealed packaging ensure virtually zero particles, organic residue, or micro-scratches.

4. What is the typical lead time and minimum order?
   Samples (up to 5 pieces) ship within 7–10 business days. Production orders (MOQ = 5 wafers) are delivered in 4–6 weeks, depending on size and custom features.

5. Do you offer custom shapes or substrates?
   Yes. In addition to standard circular wafers, we fabricate planar windows, V-groove parts, spherical lenses, and other bespoke geometries.