FAQ – 12-Inch Conductive 4H-SiC Substrate

Overview

The 12-inch conductive 4H-SiC (silicon carbide) substrate is an ultra-large diameter wide-bandgap semiconductor wafer developed for next-generation high-voltage, high-power, high-frequency, and high-temperature power electronics manufacturing. Leveraging the intrinsic advantages of SiC—such as high critical electric field, high saturated electron drift velocity, high thermal conductivity, and excellent chemical stability—this substrate is positioned as a foundational material for advanced power device platforms and emerging large-area wafer applications.

To address industry-wide requirements for cost reduction and productivity improvement, the transition from mainstream 6–8 inch SiC to 12-inch SiC substrates is widely recognized as a key pathway. A 12-inch wafer provides a substantially larger usable area than smaller formats, enabling higher die output per wafer, improved wafer utilization, and reduced edge-loss proportion—thereby supporting overall manufacturing cost optimization across the supply chain.

Crystal Growth and Wafer Fabrication Route

This 12-inch conductive 4H-SiC substrate is produced through a complete process chain covering seed expansion, single-crystal growth, wafering, thinning, and polishing, following standard semiconductor manufacturing practices:

• Seed expansion by Physical Vapor Transport (PVT):
  A 12-inch 4H-SiC seed crystal is obtained via diameter expansion using the PVT method, enabling subsequent growth of 12-inch conductive 4H-SiC boules.

• Growth of conductive 4H-SiC single crystal:
  Conductive n⁺ 4H-SiC single-crystal growth is achieved by introducing nitrogen into the growth ambient to provide controlled donor doping.

• Wafer manufacturing (standard semiconductor processing):
  After boule shaping, wafers are produced via laser slicing, followed by thinning, polishing (including CMP-level finishing), and cleaning.
  The resulting substrate thickness is 560 μm.

This integrated approach is designed to support stable growth at ultra-large diameter while maintaining crystallographic integrity and consistent electrical properties.

Metrology and Characterization Methods

To ensure comprehensive quality evaluation, the substrate is characterized using a combination of structural, optical, electrical, and defect-inspection tools:

• Raman spectroscopy (area mapping): verification of polytype uniformity across the wafer

• Fully automated optical microscopy (wafer mapping): detection and statistical evaluation of micropipes

• Non-contact resistivity metrology (wafer mapping): resistivity distribution over multiple measurement sites

• High-resolution X-ray diffraction (HRXRD): assessment of crystalline quality via rocking curve measurements

• Dislocation inspection (after selective etching): evaluation of dislocation density and morphology (with emphasis on screw dislocations)

Key Performance Results (Representative)

Characterization results demonstrate that the 12-inch conductive 4H-SiC substrate exhibits strong material quality across critical parameters:

(1) Polytype purity and uniformity

• Raman area mapping shows 100% 4H-SiC polytype coverage across the substrate.

• No inclusion of other polytypes (e.g., 6H or 15R) is detected, indicating excellent polytype control at 12-inch scale.

(2) Micropipe density (MPD)

• Wafer-scale microscopy mapping indicates a micropipe density < 0.01 cm⁻², reflecting effective suppression of this device-limiting defect category.

(3) Electrical resistivity and uniformity

• Non-contact resistivity mapping (361-point measurement) shows:

  • Resistivity range: 20.5–23.6 mΩ·cm

  • Average resistivity: 22.8 mΩ·cm

  • Non-uniformity: < 2%
    These results indicate good dopant incorporation consistency and favorable wafer-scale electrical uniformity.

(4) Crystalline quality (HRXRD)

• HRXRD rocking curve measurements on the (004) reflection, taken at five points along a wafer diameter direction, show:

  • Single, near-symmetric peaks without multi-peak behavior, suggesting the absence of low-angle grain boundary features.

  • Average FWHM: 20.8 arcsec (″), indicating high crystalline quality.

(5) Screw dislocation density (TSD)

• After selective etching and automated scanning, the screw dislocation density is measured at 2 cm⁻², demonstrating low TSD at 12-inch scale.

Conclusion from the above results:
The substrate demonstrates excellent 4H polytype purity, ultra-low micropipe density, stable and uniform low resistivity, strong crystalline quality, and low screw dislocation density, supporting its suitability for advanced device manufacturing.

12-Inch Conductive 4H-SiC Substrate

Typical Specifications

Product Value and Advantages

1. Enables 12-inch SiC manufacturing migration
   Provides a high-quality substrate platform aligned with the industry roadmap toward 12-inch SiC wafer manufacturing.

2. Low defect density for improved device yield and reliability
   Ultra-low micropipe density and low screw dislocation density help reduce catastrophic and parametric yield loss mechanisms.

3. Excellent electrical uniformity for process stability
   Tight resistivity distribution supports improved wafer-to-wafer and within-wafer device consistency.

4. High crystalline quality supporting epitaxy and device processing
   HRXRD results and the absence of low-angle grain boundary signatures indicate favorable material quality for epitaxial growth and device fabrication.

Target Applications

The 12-inch conductive 4H-SiC substrate is applicable to:

• SiC power devices: MOSFETs, Schottky barrier diodes (SBD), and related structures

• Electric vehicles: main traction inverters, onboard chargers (OBC), and DC-DC converters

• Renewable energy & grid: photovoltaic inverters, energy storage systems, and smart grid modules

• Industrial power electronics: high-efficiency power supplies, motor drives, and high-voltage converters

• Emerging large-area wafer demands: advanced packaging and other 12-inch-compatible semiconductor manufacturing scenarios