SOI Wafer Silicon-on-Insulator Wafer 4inch 5inch 6inch 8inch 100 111 P Type N Type
Product Details:
Place of Origin: | China |
Brand Name: | ZMSH |
Model Number: | SOI Wafe |
Detail Information |
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Soi Handle Layer: | Contact Us | Substrate: | SOI Wafer |
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Ttv: | <10um | Gan Layer Thickness: | 1-10 µm |
Polish: | Double/Single Side Polish | Orientation: | <100> |
Highlight: | 8 inch SOI Wafer,6 inch SOI Wafer,5 inch SOI Wafer |
Product Description
SOI Wafer Silicon-on-Insulator Wafer 4inch 5inch 6inch 8inch (100) (111) P Type N Type
Description of SOI Wafer:
SOI wafer refers to a thin layer of silicon single crystal overlaid on an insulator made of silicon dioxide or glass (hence the name "silicon on insulation lining", often referred to as SOI for short). Transistors built on a thin layer of SOI can operate faster and consume less power than those built on a simple silicon chip. In semiconductor manufacturing, silicon-on-insulator (SOI) technology is the fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS). The choice of insulator depends largely on the intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer and topmost silicon layer also vary widely depending on the application.
The character of SOI Wafer:
- Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at matched performance
- Resistance to latch-up due to complete isolation of the n- and p-well structures
- Higher performance at equivalent VDD. Can work at low VDDs[5]
- Reduced temperature dependency due to no doping
- Better yield due to high density, better wafer utilization
- Reduced antenna issues
- No body or well taps are needed
- Lower leakage currents due to isolation thus higher power efficiency
- Inherently radiation hardened (resistant to soft errors), reducing the need for redundancy
Product Structure of SOI Wafer:
Diameter | 4" | 5" | 6" | 8" | |
Device Layer | Dopant | Boron, Phos, Arsenic, Antimony, Undoped | |||
Orientation | <100>, <111> | ||||
Type | SIMOX, BESOI, Simbond, Smart-cut | ||||
Resistivity | 0.001-20000 Ohm-cm | ||||
Thickness (um) | >1.5 | ||||
TTV | <2um | ||||
BOX Layer | Thickness (um) | 0.2-4.0um | |||
Uniformity | <5% | ||||
Substrate | Orientation | <100>, <111> | |||
Type/Dopant | P Type/Boron , N Type/Phos, N Type/As, N Type/Sb | ||||
Thickness (um) | 200-1100 | ||||
Resistivity | 0.001-20000 Ohm-cm | ||||
Surface Finished | P/P, P/E | ||||
Particle | <10@.0.3um |
Structure of SOI wafer:
Applications of SOI Wafer:
Our customized SoL solutions are used in the following fields:
- Advanced pressure sensors
- Accelerometers
- Gyroscopes
- Microfluidics/flow sensors
- RF MEMS
- MEMS/optical MEMS
- Optoelectronics
- Smart metering
- Advanced analog ICs
- Microphones
- Luxury wristwatches
End Markets:
- Telecommunications
- Medical
- Automotive
- Consumer
- Instrumentation
Application picture of SOI Wafer:
Packing and Shipping:
FAQ:
1.Q: What is the dielectric constant of silicon on insulators?
A: The dielectric constant for commonly used silicon materials are: Silicon dioxide (SiO2) - dielectric constant = 3.9. Silicon nitride (SiNx) - dielectric constant = 7.5. Pure silicon (Si) - dielectric constant = 11.7
2.Q:What are the advantages of SOI wafers?
A: SOI wafers have greater resistance to radiation, making them less prone to soft errors. The higher density also increases the yield, thus improving wafer utilization. Additional advantages of SOI wafers include a reduced dependency on temperature and fewer antenna issues.
Product Recommend:
1. GaN-on-Si(111) N/P T type Substrate Epitaxy 4inch 6inch 8inch For LED Or Power Device
2. N-type SiC On Si Compound Wafer