What is self-aligned quadruple patterning (SAQP) technology?

Multi-patterning is a technique to overcome lithographic limitations in chip manufacturing. Today's single exposure, 193nm wavelength lithography reaches its physical limit at 40nm half pitch. Multi-patterning enables chip manufacturers to image IC designs at 20 nanometers and below.

Broadly, multi-patterning has two main categories: pitch splitting and spacers. Pitch splitting is an umbrella term that includes double patterning and triple patterning techniques. Meanwhile, spacers include self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). Both pitch splitting and spacer techniques can extend to octuple patterning.

The first type, pitch splitting, is primarily used in logic. The most common form of pitch splitting is double patterning. In design, double patterning almost always refers to the litho-etch-litho-etch-litho-etch (LELE) pitch splitting process. In wafer fabrication, LELE requires two independent lithography and etching steps to define a single layer. According to Sematech, LELE can reduce pitch by 30%. However, LELE can be costly as it doubles the process steps in lithography.

Initially, this technique separates layouts that cannot be printed with a single exposure into two lower density masks. Then, it employs two separate exposure processes. This forms two rougher patterns. They are combined and overlaid to enable finer imaging on the wafer.

LELE (i.e., double patterning) poses new layout, physical verification, and debugging requirements for designers. For instance, in design, colors are assigned to mask layers based on spacing requirements. Mask layers are segmented or decomposed into two new layers from the original drawn layout.

A key decision in methodology is whether designers want to pursue a "colorless" design flow. Another option is a two-color flow, where designers lay out two masks, selecting among several decomposition options. Of course, any design flow requires trade-offs.

At the 20-nanometer node, foundries are employing several different double patterning design flows. One of the more common flows actually does not require the design team to decompose its layers into two colors. However, in certain cases, designers may want to know what the color assignment is. While this sounds reasonable, seeing double patterning colors can potentially decrease debugging efficiency.

Meanwhile, at the 10nm node, chip manufacturers may need to turn to another pitch splitting technique—triple patterning. One form of triple patterning is litho-etch-litho-etch-litho-etch (LELELE). LELELE is similar to LELE. In wafer fabrication, LELELE requires three independent lithography and etching steps to define a single layer.

In design, triple patterning necessitates breaking down the original layer into three masks. The shapes of the three masks combine during manufacturing to form the final shape. Triple patterning may seem harmless from the outside, but potential chaos lies within. Building EDA software algorithms to automatically decompose, color, and check layers with triple patterning is a challenge. Triple patterning violations can be very complex, and debugging can be difficult.

Meanwhile, spacers are the second main category of multi-patterning. It is also known as SADP and SAQP. SADP/SAQP was previously used to extend NAND flash to the 1xnm node and is now entering the logic field.

SADP is a form of double patterning. It is sometimes called pitch division or sidewall-assisted double patterning. The SADP process uses one lithography step along with additional deposition and etching steps to define features similar to spacers. In the SADP process, the first step is to form mandrels on the substrate. Then, a deposition layer covers the pattern. The deposition layer is then etched away, forming spacers. Finally, the top portion undergoes chemical mechanical polishing (CMP) steps.

SAQP is essentially two cycles of sidewall spacer double patterning technology. Simple patterns, including those in flash or finFET, are accomplished in SADP or SAQP. In this technique, parallel lines are formed first, followed by cutting. Meanwhile, the metal layers in DRAM and logic chips are more complex and cannot be achieved through SADP/SAQP. These metal layers require LELE. The design flexibility of SADP/SAQP is also lower than LELE, while LELE-type technologies require via patterning.

SAQP stands for Self-Aligned Quadruple Patterning.

According to available information, Self-Aligned Quadruple Patterning (SAQP) is the most widely used technique for patterning features with pitches smaller than 38 nm, expected to achieve pitches down to 19 nm. It essentially integrates multiple process steps and has been employed in the patterning of FinFET and 1X DRAM fins. These steps, as depicted in Figure 1, allow lines initially drawn 80 nm apart to result in lines spaced 20 nm apart (effectively achieving 10 nm resolution). This is significant as it far surpasses the resolution of any mass production lithography tool, including EUV (which achieves 13 nm resolution).

The process naturally divides features into three groups: core, shell, and boundary (see Figure 2). The shell naturally forms rings that require cutting. Similarly, the boundary forms a grid that also needs to be segmented. Therefore, the SAQP process must conclude with a lithography step, which cuts or trims the previously defined shell and boundary features. In contrast, the older SADP process only had two groups: core and boundary.

In another variant of the SAQP process flow (see Figure 3), the shell features are actually the remaining first spacer material, while the core and boundary are different materials, either the substrate or gap-fill material. Hence, they are represented with different colors in Figure 2. The fact that they are different materials implies that they can be selectively etched. This offers opportunities for achieving some challenging patterning.

A particularly useful application is the combination of minimum pitch and 2x minimum pitch features. This combination is typically prohibited in single exposures with k1 < 0.5. One particularly daunting combination is minimum pitch lines with 2x minimum pitch interruptions (see Figure 4, left). The diffraction pattern of the interruptions is much weaker compared to that of the lines themselves because they occupy a much smaller area. Their performance also deteriorates much faster under defocus. This combination also cannot be fixed with assist features since there is no space to insert them to achieve minimum pitch lines. On the other hand, through selective etching, the mask features can pass through the intervening lines (see Figure 4, right). This greatly simplifies the cutting and avoids potential edge placement errors that may occur when cutting separately in two locations.

For selective etching, three masks are necessary - one to define the separate A/B regions, the second mask for A selective etching, and the third mask for B selective etching. However, selective etching (combined with SAQP) also allows for larger overlapping tolerances and a minimum number of masks, thus enabling the combination of minimum line pitch and interruptions at twice the minimum line pitch, making multi-patterning easier to handle.

In summary, all self-aligned multi-patterning processes include the following steps:

1. Printing mandrel tracks.
2. Growing sidewalls on the printed mandrel patterns.
3. Removing the mandrel patterns.
4. Developing the final manufactured patterns between the sidewalls.
5. Adding dielectric blocks to achieve the desired tip-to-tip spacing in the final target.

6. As we progress towards more advanced technology nodes, patterning the critical back-end-of-line (BEOL) metal layers with more aggressive pitches, such as 32 nanometers, becomes exceedingly challenging. Typically, trenches are created in these BEOL layers, which are then filled with metal in the final metallization step. To generate interruptions within continuous trenches, vertical blocking layers perpendicular to the trenches are added, forming small metal tip-to-tip spacings.

   Within the industry, various options have been considered for patterning the most aggressive BEOL layers and blocks. One option is to combine immersion lithography with what's known as Metal Line Self-Aligned Quadruple Patterning (SAQP), along with triple patterning of the block layers. However, this option requires triple block masks and a triple lithography process, which adds to the cost and complexity of the proposed solution. Another option is to directly use Extreme Ultraviolet Lithography (EUVL) to pattern the BEOL metal layers in a single exposure. While this direct EUVL integration process is straightforward and cost-effective, the fidelity (such as the shape) and variability of the patterns, as well as mask fabrication, are expected to be highly challenging, especially for very small tip-to-tip spacings.