What's the orientation of SiC substrate?

Since the actual crystal is not infinite, it will eventually end up in a plane. Semiconductor devices are fabricated on or near the surface, so the properties of the surface may affect the properties of the device. These surface properties are generally described by crystal plane or crystal direction.

1. Orientation of SiC substrate

Crystal orientation: The direction indicated by the line between any two atoms/molecules/ions in a crystal cell is called crystal orientation.
 

Crystal Plane: The plane formed by a series of atoms/molecules/ions is called the crystal plane.
 

Crystal orientation index: Take a certain point O of the unit cell as the origin, set the coordinate axis X/Y/Z through the origin O, take the length of the lattice vector of the unit cell as the length unit of the coordinate axis, make a straight line OP through the origin O, require P point to be the closest to O point, and make it parallel to the crystal direction AB, determine the three coordinate values of P point, convert the three values into the minimum integer u, v, w, plus square brackets, [uvw] is the crystal orientation index of AB to be determined. If one of u, v, or w is negative, just put the negative sign above the number. A crystal direction in which all the directions indicated by the index are consistent and parallel to each other.

Crystal orientation group: Crystal atoms are arranged in the same set of crystal to known as the crystal to the family, such as the cubic crystal system, a/b/c three values are the same, [111] crystal wafer to a total of eight to the clan ([111], [111], [1-11] and [11-1], [1-11], [- 11-1], [1-1-1], [1-1-1]). Denote this orientation group by <111>. Similarly, the <100> orientation group contains six orientations: [100],[010],[001],[-100],[0-10] and [00-1]. If it is not cubic, the orientation group may be different by changing the order of the orientation index.

2. Schematic diagram of wafer C and Si face wafer diameter, Primary Flat, Secondary Flat, and laser marking position.

3. Why <100> crystalline substrates are often used to manufacture power devices such as MOSFETs?

Power devices are generally surface channel devices, and the density of states of surface defects greatly influences the threshold voltage and reliability. The atomic surface density of (100) crystal surface is the smallest, and the corresponding atomic surface density of states is also the smallest. There are fewer unsaturated bonds on the surface of the device, and fewer defects are generated when the device surface is oxidized.
 

Due to the small density of (100) crystal face, its thermal oxidation and etching rate is relatively fast, the process leaders of <100> crystal direction process research is also more;
The <110> crystal direction is the direction with the highest electron mobility in silicon wafers, because the atoms in the <110> crystal direction are relatively closely arranged, and the electrons will encounter fewer obstacles when moving in this direction, so the electron mobility is high. However, the atoms in the <100> crystal direction are arranged loosely, and the electrons will be hindered by many obstacles when moving in this direction, so the electron mobility is relatively low. Although <110> orientation silicon wafers have better performance in some aspects, they are not often used because of their tight lattice structure and the high cost and technical difficulty of cutting silicon wafers into <110> orientation wafers.
 

In some device layout designs, the cell direction or gate polycrystalline direction is not perpendicular to the scripting channel but is at a 45 degree Angle with the scripting channel, the purpose is to make the channel direction of the crystal direction to <110>, increase the mobility of charge carriers, reduce the loss, in addition to different layout direction, the overall stress consistency of the wafer is also beneficial. Later, there were more and more groove-type devices, and the direction of channel charge carriers was perpendicular to the crystal plane, so it was of little significance to change the other direction in terms of mobility improvement.

Before 40nm, CMOS processes tend to use <100> crystal orientation substrates. To 28nm, in order to maximize the mobility of PMOS, the industry uses <110> crystal orientation substrate. In this direction, the PMOS channel is the most sensitive to compressive stress, so the mobility can be improved to the greatest extent. The 28nm process will use the source leakage germanium silicon stress technology to optimize the hole mobility, which can be improved by about 20% in the <100> crystal direction. Although <110> orientation silicon wafers have better performance in some aspects, due to their tight lattice structure, silicon wafers are more expensive and technically difficult to cut into <110> orientation wafers.

4. Why SiC power devices are often made of 4H-SiC crystal structure and <0001> wafers?

Among the various crystal types of SiC, 3C-SiC has the lowest bond energy, the highest lattice-free energy, and easy nucleation, but it is in the metastable state, with low stability and easy solid phase transfer. Phase transition is more likely to occur under the influence of external conditions. Therefore, by changing the external conditions, 3C-SiC can undergo phase transformation and become other crystal forms.

The following is a specific comparison of the performance difference between 4H-SiC and 6H-SiC to know why SiC power devices commonly use 4H-SiC crystal structure:

The main differences between 4H SiC and 6H-SiC lie in their crystal structures, physical properties, and electrical properties. 4H SiC has an ABCB stacking order and a higher symmetry compared with the ABABAB stacking of 6H-SiC. This symmetry difference affects the crystal growth process, resulting in a smaller defect density of 4H-sic and better crystal quality. 4H-SiC exhibits higher thermal conductivity along the C-axis and higher carrier mobility, making it suitable for high-frequency and high-power applications such as MOSFETs, Schottky diodes, and bipolar junction transistors. However, 6H-SiC has lower deep-level defects and lower carrier recombination rate, which is more suitable for high-quality substrate applications, such as high-quality substrate applications, epitaxial growth, and the manufacturing of electronic devices. The choice between the two crystal structures depends on the specific requirements of the semiconductor device and its intended application.

5. Why is the wafer orientation of SiC power devices often <0001>?

According to the crystal orientation analysis of silicon, the crystal structure of 4H-SiC <0001> has the following advantages:

Crystal structure advantage:

The wafer structure of SiC material has a good lattice match in the <0001> crystal direction, which enables high crystal quality and wafer integrity in the wafer growth and manufacturing process.

The <0001> orientation can form a Si-C bond surface with a low density of interfacial states, which is conducive to obtaining a high-quality SiC-SiO2 interface.

The surface of <0001> crystal direction is relatively flat, which is conducive to obtaining high-quality epitaxial film growth. In addition, the density of carbon atoms in the crystalline direction of <0001> is higher, which is conducive to obtaining higher breakdown electric field intensity, which is very important to ensure the insulation reliability of the device.

Thermal conductivity advantage:

SiC material has a very high thermal conductivity, which enables more efficient heat dissipation during the operation of power devices. The <0001> SiC wafer has high thermal conductivity, which further enhances the heat dissipation performance of the chip and helps to improve the power density and reliability of the power device.

Device performance advantages: The <0001> SiC wafer can achieve lower leakage current and higher breakdown voltage. In addition, the SiC wafer also has higher carrier mobility and a large spontaneous polarization effect, which can be used to enhance the electron density of the MOSFET channel, improve the conduction current in the conduction state, and help to improve the switching speed and operating frequency of the device.